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一、简介
JESD204是一种连接数据转换器(ADC和DAC)和逻辑器件的高速串行接口,支持高达 12.5 Gbps串行数据速率,并可确保 JESD204
链路具有可重复的确定性延迟。随着高速ADC跨入GSPS范围,与FPGA(定制ASIC)进行数据传输的首选接口协议是JESD204B。
JESD204B标准是一种分层规范。规范中的各层都有自己的功能要完成。
①应用层
支持JESD204B链路的配置和数据映射。
②传输层
实现转换样本与成帧未加扰八位字之间的映射。它获取原始的样本数据并将其打包成某种方式,以jesd204b的标准,并将此数据分发到不同的通道。
③数据链路层
可选加扰的八位字编码成10位字符。该层也是产生或检测控制字符的地方,目的是监视和维护通道对齐。
④物理层
即串行器/解串器(SERDES)层,负责以线路速率发送或接收字符。该层包括串行器、驱动器、接收器、时钟和数据恢复电路。
注:加扰层可以选择性地获取八位字并进行加扰或解扰,以便通过延展频谱尖峰来降低EMI效应。加扰在发送器中完成,解扰在接收器中完成。
每个链路最多支持32个通道,每个通道可以传输高达12.5Gb/s的原始数据,不仅描述了如何从A到B获取位,而且还对它描述的位表示意义如何将样本映射到这些高速通道,可以进行数据的同步传输。
Subclass 0:
不支持确定性延迟
Subclass 1:
支持确定性延迟,利用外部的SYSREF作为时钟信号。
基本思想是在SYSREF的上升沿之后,器件时钟的下一个上升沿称为时间参考点,内部分频器可能会被重置为起始值,有时需要多个SYSREF信号来复位
Subclass 2:
支持确定性延迟,利用~SYNC作为时钟信号;
~SYNC的作用:请求初始化序列,对其数据、串行器和解串器,此方法不适用于更高频率。