preface ： Welcome , Predestined person !
1. Verification technology based on Dynamic Coverage
Coverage is right RTL Percentage of coverage achieved after verification of design functions
The inspection process must meet the requirements of integrity and correctness , No redundant labor
To minimize verification effort , Use coverage to measure which functions of a design have been tested , Which functions have not been tested
The functional coverage is defined by the verification engineer , Used to measure whether the design specification is correctly realized , The specific content is reflected in the verification plan
Function coverage is used to check the application scenarios of the design , boundary condition , Whether special variables or design conditions have been correctly tested or confirmed
2. Coverage type
2.1 Coverage type ：RTL Code coverage
* The easiest way to measure validation progress is to use code coverage , No extra HDL code , The tool will automatically help you complete the design of code coverage by analyzing source code and adding hidden code ;
* Measure which design specifications are covered in the test case verification RTL Implemented in , The verification plan cannot be measured
* Row coverage （ Line Coverage): How many lines of code have been executed
* Finite state machine coverage （ FSM Coverage): Which states and state transitions in the state machine have been accessed
* Path coverage （ Path Coverage): What has been executed in the path through code and expressions ,RTL Path branches in code （if-else sentence ）
* Flip coverage （ Toggle Coverage): Which single bit variables from 0 Jump to 1, And from 1 Jump to 0
* Expression coverage （ Expression coverage）:RTL Conditional expressions in code , for example if(a&b&c)
2.2 Coverage type ： Function coverage
Functional coverage is closely related to the design intent , Sometimes called “ Specification coverage ”, Code coverage is a measure of the implementation of the design . Imagine a code block being missed in the design . Code coverage cannot find this error , But the function coverage is OK .
100% Code coverage of does not mean 100% Functional coverage of .
2.3 Coverage type ： assertion coverage
Assertion Coverage assertion coverage
* Assertions are declarative code , For inspection RTL Relationship between signals in code
* Assertions can use procedural code or use Systemverilog Assertions
* Assertions can check the value of a signal or the state of a design
* cover property sentence
2.4 Coverage type ： Target coverage
Target coverage refers to the target value of verification points specified in the verification plan . In the validation plan , When the actual coverage of the verification point does not reach 100% When , Explain that the verification work has not completed the target scheme . fall short of 100% The project needs to be fully verified by adding test cases or modifying constraints .
3. Function coverage
3.1 A simple example of function coverage
//systemverilog Green Book // Example 9.2 A simple function coverage program automatic teat (busifc.TB ifc)
class Transaction; rand bit [31:0] data; rand bit [ 2:0] port;// Eight ports （port） data
endclass covergroup Covport; coverpoint tr.port;// Measurement coverage endgroup initial begin
Transaction Tr; Covport ck; ck = new();// Instantiation group tr = new();
repeat(32)begin// function 32 cycle assert(tr.randmoize);// Create a transaction
ifc.cb.port<=tr.port;// And send it to the interface ifc.cb.data<=tr.data; ck.sample();// Collection coverage
@ifc.cb;// Wait for a cycle end end endprogram
use VCS Running Report !
3.2 Define override group
Override groups can be found in the program , Defined in module or class . In all cases , Coverage groups can only be sampled after explicit instantiation . If the override group is defined in a class , Use the original name when instantiating , Don't use another name .
//systemverilog Green Book // Example 9.5 Define function coverage in class class Transactor; Transaction tr;
mailbox mbx_in; covergroup Covport; coverpoint tr.port;// Measurement coverage endgroup
function new(mailbox mbx_in); Covport = new();// Instantiate coverage group this.mbx_in=mbx_in;
endfunction task main; forever begin tr=mbx_in.get;// Get next transaction
ifc.cb.port<=tr.port;// Send to the design to be tested ifc.cb.data<=tr.data; Covport.sample();// Collection coverage
end endtask endclass
covergroup
* Specification of package coverage model
* each covergroup Include the following
A clock event , For synchronous sampling of building cover points
A set of coverage points
Cross coverage between coverage points
Optional formal parameters
Coverage options
* Covergroup It is a user-defined structure type
* After defining the type , It can be instantiated many times in different programs
* Follow class similar , After definition , You can use constructor new() generate covergroup Instance of
* covergroup Can be defined in module, program, interface or class in
* One covergroup Can contain one or more coverage points
A coverage point can be a variable or an expression
Each coverage point has a group bins value , This value is related to the sampled variables or the conversion of variables
Bins The value of can be defined by the user , Or yes EDA Tool auto generation
Coyergroupe The name of should be clear , The function of coverage can be confirmed by name. It is best to be consistent with the verification plan
Define coverage points ： Signals and expressions
* Sampling data
* How to collect coverage information ?
Variables and expressions are specified in the coverage point , System Verilog Created a group bins, Used to record those sampled values
bins It is a measure of functional coverage
At the end of each simulation , The generated database contains all the data after sampling bins
EDA The analysis tool can read this database , Generate a coverage report , Which part of the design is covered in the report , And the total coverage value
* private bins And total coverage
Calculate the coverage of a coverage point , First, confirm the total number of possible values
Define coverage points ：bins
Sampling data ：bins
* private bins And total coverage
Systemverilog Automatically create for overlay points bins
One N The expression of bit has 2N Valid values
One 3 Variable of bits port have 8 Valid value
*
Limit auto generated bins Quantity of
cover group option auto_ bin max Specify automatic generation bins Maximum quantity of , The default value is 64bins
Define coverage points ： expression
Define coverage points ： Conditional coverage
Use keywords iff Add conditions for coverage points
Define coverage points ： Status transfer override
Define coverage points ： Cross coverage
Parametric coverage ： Provide code reusability
Postscript
： Last four days , Helped grandpa build a colored steel tile shed , Experienced the housing construction of rural families . From purchasing materials to intermediate construction to final completion , There are many conflicting ideas . They often solve various problems according to their own experience , There are several points that make the craftsman , Grandpa and others accept and implement . The last day , Be paid to do other things , Sure enough, they wasted some materials again , As a result, grandpa also said that the craftsman didn't do it well , When I see , It can't be reworked . We can experience the feudal ideology of rural people , Communication with low quality makes me have to escape from rural life . Do not know why? , I can't accept the dirty words of my family , It ended on the last day , Help Grandpa install the TV pot , Here comes my niece , I don't know why , Grandpa scolded her ：NMRLD, forget it , Try your best . Rush rush rush !
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