<> summary
* Memory classification
* Classification by storage medium
(1) Semiconductor memory TTL( Low degree of integration High power consumption , Fast speed ),MOS( High integration Low power consumption );
(2) Magnetic surface memory head , Carrier magnet ;
(3) Magnetic core memory Hard magnetic material , Ring element ;
(4) Optical disk storage laser , Magneto optic material ;
summary ： Semiconductor memory volatility ; Magnetic surface memory , Magnetic core memory , Optical disk memory nonvolatile ;
* Classification by access mode
(1) The access time is independent of the physical address （ Random access ）
Random access memory Readable and writable during program execution ;
read-only memory Read only during program execution ;
(2) The access time is related to the physical address （ Serial access ）
Sequential access memory magnetic tape ;
Direct access memory disk ;
* Classification by role in computer
* Memory hierarchy
* Relationship between three main characteristics of memory
* cache - Main memory hierarchy and main memory - Auxiliary storage level
<> Main memory overview
*
Basic composition of main memory
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Main memory sum CPU Contact
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Allocation of storage unit address in main memory
12345678H How is this data stored in main memory ?
High byte ： Low address in high order , High address in low order ;
Low byte ： High address in high order , Low address in low order ;
Examples ：
analysis ：
introduce 1
First look at a simple question ：
There is a 1MB Large capacity memory , Word length 32 position , ask ： Byte addressing , Addressing range of word addressing and respective addressing range size ?
If addressed by byte , be
1MB = 2 ^10KB = 2 ^20B 1 byte =8bit=1B 2 ^20B/1B = 2 ^20
Address range is 0~(2 ^20)-1, That is to say, we need 20 Only the root address line can complete the alignment 1MB Spatial coding , So the address register is 20 position , The addressing range size is 2 ^20=1M;
If addressing by word , be
1MB = 2 ^10KB = 2 ^20B 1 byte =32bit=4B 2 ^20B/4B = 2 ^18
Address range is 0~(2 ^18)-1, Which means we need at least 18 Only the root address line can complete the alignment 1MB Spatial coding . Therefore, the addressing range size of word addressing is 2 ^18;
Distinguish two different concepts of addressing space and addressing range , The addressing range is only a numeric range , Addressing without units
The size of the range is obviously a number , Refers to the size of the addressing interval, while the addressing space refers to the maximum capacity that can be addressed , Unit general use MB,B To show ; The addressing range in this question is 0~(2^20)-1, Address space is 1MB, Addressing size 1M;
M Unit of quantity 1024=1K,1024K=1M MB Refers to the capacity 1024B=1KB,1024KB=1MB.
introduce 2
There is a machine with 24 Root address line , Addressing by byte , Find its addressing range ?
The addressing range is 0~(2 ^24)-1, Addressing size 2 ^24=2 ^4M, Namely 16MB;
introduce 3
There is a machine with 24 Root address line , Its word length is 16 position , Word addressing , Find its addressing range ?
The word is encapsulated with bytes , To ensure that each byte or data has its own number , Then we need to sacrifice part of the address line to achieve .16 Bit word length machine , Each word represents 2 Bytes , use 1 Bit address lines can be distinguished , This can be compared to “ Each bag contains two buns , And now I just number the bags , If you want to find out whether the steamed stuffed bun in the bag is the first or the second, you must take out one 0 and 1 To indicate the first or second steamed stuffed bun ”. Thus, the number of data lines representing the word address is only left 24-1=23 Bit . So the addressing range becomes 0~(2^23)-1, Addressing size 2
^23=2 ^3M, Namely 8MW Yes ;(W Representative words )
introduce 4
There is a machine with 24 Root address line , Its word length is 32 position , Word addressing , Find its addressing range ?
The word is encapsulated with bytes , To ensure that each byte or data has its own number , Then we need to sacrifice part of the address line to achieve .32 Bit word length machine , Each word represents 4 Bytes , use 2 Bit address lines can be distinguished , This can be compared to “ Each bag contains four steamed stuffed buns , And now I just number the bags , Do you have to take out the first one or the second one 0 and 1 To indicate the first or second steamed stuffed bun, etc ”. Thus, the number of data lines representing the word address is only left 24-2=22 Bit . So the addressing range becomes 0~(2^22)-1, Addressing size 2
^22=2 ^2M, Namely 4MW Yes ;
*
Technical indicators of main memory
(1) storage capacity
The total number of bits of binary code stored in main memory ;
(2) Storage speed
Access time ： Memory access time to read time or write time ;
Access cycle ： Two consecutive independent accessor operations ( Read or write ) Minimum interval required ;
Access cycle > Access time
(3) Memory is bandwidth Company position / second ;
<> Introduction to semiconductor memory chip
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Basic structure of semiconductor memory chip
Film selection line ：（ Low level active selection ）
read / Write control line ：
Calculate chip capacity using address line and data line ：
Address line （ one-way ） data line （ two-way ） Chip capacity 10 4 (2 ^10*4)1K*4 position 14 1 16K*1 position 13 8 8K*8 position
Function of memory chip line selection ：
It can make a chip or a write chip work at the same time ;
example ：
analysis ：
Each group 8 individual 16K *1 Bit memory chip , Simultaneous work , constitute 16K *8 Bit memory chip . There are four groups , Total represents storage 64K, use 32 individual 16K *1 Bit memory chip . first group 0 ~
16K-1, Group 2 16K ~ 32K-1, Group 3 32K ~ 48K-1, Group 4 48K ~ 64K-1; So it constitutes 64K *8 Bit memory ;
When the address is 65535 Time , express 64K-1, Group 4 8 The selection of films is valid , Select for low level . The other three groups are high-level invalid ;
*
Decoding driving mode of semiconductor memory chip
(1) Line selection method
(2) Re legal
<> Random access memory （RAM）
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static state RAM（SRAM）
(1) static state RAM Read operation of basic circuit
(2) static state RAM Write operation of basic circuit
(3) static state RAM Chip example
Intel 2114 External characteristics
Intel 2114 RAM matrix （64 *64） read
Intel 2114 RAM matrix （64 *64） write
*
dynamic RAM（DRAM）
(1) dynamic RAM Basic unit circuit
Three tube ：
Read out is opposite to the original information ;
The writing is the same as the input information ;
Single tube ：
When reading out, the current of the data line is 1;
When writing Cs Charging for 1, Discharge as 0;
(2) dynamic RAM Chip example
Three tube dynamic RAM chip (Intel 1103) read
Three tube dynamic RAM chip (Intel 1103) write
Single tube dynamic RAM chip Intel 4116(16K *1 position ) External characteristics
notes ： need 14 Root address line , But in fact, only 7 Root address line , So it needs to be divided into two times ;
Intel 4116 chip read principle
Intel 4116 chip write principle
(3) dynamic RAM Refresh
Refresh is related to row address
① Refresh set （ The access cycle is 0.5μs）
Centralized refresh is within a specified refresh cycle , Refresh all storage units row by row for a period of time , You must stop reading at this moment / Write operation . use 0.5μs
*128=64μs Right time 128 Refresh row by row , Because of this 64μs The time cannot be read / Write operation , Therefore, it is called “ Dead time ” Or deposit access “ dead zone ”. Since the access cycle is 0.5μs, Refresh cycle is 2ms, Namely 4000 Access cycles .
Add one thing ： Why can't refresh and access be in parallel ?
Because the memory is a set of address decoding and chip selection devices , Refresh and access have similar processes , It selects a row —— Film selection during this period , Address line , All the address decoders are occupied . Similarly , Refresh operations cannot be performed in parallel —— It means you can only brush one line at a time .
② Decentralized refresh （ The access cycle is 1μs）
Decentralized refresh means that the refresh of each row of storage units is completed within each access cycle . among , Put the access cycle of the machine tc Divided into two sections , First half tM Used to read / Write or maintain information , Second half tR
Used to refresh . That is, a refresh operation is bound after each access operation . Extended access cycle , So the access cycle becomes 0.5μs + 0.5μs
=1μs. However, due to the binding with access operation , There is no need to give a special period of time to refresh . such , Every 128 Read operations , Will put 0-127 Refresh all rows . So every 128μs
You can refresh all the memory chips , That is, the refresh cycle is 1μs×128=128μs Much shorter than 2ms, And there is no stop reading /
Written dead time , But the access cycle is long , The speed of the whole system is reduced （ Refresh cycle of decentralized refresh 128μs , Actually, it doesn't need to be so frequent , Will lead to waste ）;
③ Asynchronous refresh （ Combination of decentralized refresh and centralized refresh ）
It can be shortened “ Dead time ”, And make full use of the maximum refresh interval of 2ms Characteristic , The specific operation is ： stay 2ms Inner pair 128 Refresh each line , Every 15.6μs Refresh a row (2000μs /
128≈15.6μs), The refresh time of each row is still 0.5μs. such , Refreshing a row can only stop one access cycle , But for each line , Refresh interval is still 2ms, Died at 0.5μs.（ Relative to each paragraph , Centralized refresh , Relatively speaking , Distributed refresh ）. If will
DRAM
Refresh schedule for CPU Decoding stage of instructions , Because of this stage CPU Do not access memory , Therefore, this scheme not only overcomes the monopoly of decentralized refresh 0.5μs For refresh , The disadvantage of lengthening the access cycle and reducing the system speed , There will be no centralized refresh memory access “ dead zone ” problem , The working efficiency of the whole machine is fundamentally improved ;
3. dynamic RAM And static RAM Comparison of
<> read-only memory （ROM）
brief introduction ：
* Mask ROM（MROM）
At the intersection of row and column selection lines MOS Guan Wei 1;
None at the intersection of row and column selection lines MOS Guan Wei 0;
* PROM（ One time programming ）
* EPROM（ Multiple programming ）
* EEPROM（ Multiple programming ）
* Flash Memory（ Flash memory ）
<> Memory and CPU Connection of
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Expansion of memory capacity
(1) Bit extension （ Increase storage word length ）
use 2 slice 1K *4 Bit memory chip composition 1K *8 Bit memory （10 Root address line ,8 Root data line ）
(2) Word expansion （ Increase the number of stored words ）
use 2 slice 1K *8 Bit memory chip composition 2K *8 Bit memory （11 Root address line ,8 Root data line ）, Different working utilization 1 Select one of the chips from the root address line
0 10 individual 0~10 individual 1 First piece ;
1 10 individual 0~10 individual 1 Second piece ;
(3) word , Extension bit
use 8 slice 1K *4 Bit memory chip composition 4K *8 Bit memory （21 Root address line ,8 Root data line ）, each 2 slice 1K *4 Bit composition 1K *8 Bit chip , need 4 group ;
00 10 individual 0~10 individual 1 first group ;
01 10 individual 0~10 individual 1 Group 2 ;
10 10 individual 0~10 individual 1 Group 3 ;
11 10 individual 0~10 individual 1 Group 4 ;
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Memory and CPU Connection of
Connection of address line
Connection of data cable
read / Write command connection
Connection of chip selection line
Reasonable selection of memory chip
other sequential , load
Main memory address space allocation ：
System program area ：6000H~67FFH
User program area ：6800H~6BFFH
(1) Write the corresponding binary code
(2) Determine the number and type of chips
(3) Assign address line
(4) Determine chip selection signal
74138 Introduction to decoder
A,B,C Input port , Enter binary number ;
Y0~Y7 Output port , Output decimal number ;
G1,G2A,G2B Chip selection port , When this is 100 Time chip gating , Otherwise it will not work ;
(1) Write out the corresponding binary address code
(2) Determine the number and type of chips
(3) Assign address line
(4) Determine chip selection signal
(1) Write out the corresponding binary address code
(2) Determine the number and type of chips
(3) Assign address line
(4) Determine chip selection signal
<> Verification of memory
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Minimum distance of coding
Minimum difference of binary digits between any two combination codes ;
Coded error correction , The ability of error detection is related to the minimum distance of coding ;
Hamming code is a code with one bit error correction ability ;
*
Composition of Hamming code
Hamming codes use parity check , Group check ;
The grouping of Hamming codes is a non division method ：
Divided into three groups , Each group has 1 Bit check bit , Total includes 4 Digit data bit ;
Why three groups ：
Write the corresponding binary code ：
1 001
2 010
3 011
4 100
5 101
6 110
7 111
therefore ,001 Representative 1 For the first group ,010 Representative 2 For the second group ,100 Representative 4 For the third group .011 On behalf of 1 And section 2 Group common part ;
How many detection bits need to be added to the composition of Hamming code ：2k>=n+k+1;
Position of detection bit ：2i (i=0,1,2,3,……);
XOR ： XOR different bit truth (1), The same or the same is true (1);
*
Error correction process of Hamming code
The decimal value corresponding to binary multiple is the error bit ;
Because the fourth digit is the check digit , Wrong , You can't correct it ;
check ： Different from parity , Error correction process , XOR for even check , Parity check with or ;
<> Measures to improve the speed of memory access
* Using high-speed devices ;
* Adopt hierarchy Cache - Main memory ;
* Adjust main memory structure ;
Technology