<>VHDL Realize full adder
1. One bit full adder
Full adder is a binary addition circuit that can calculate low carry , One bit full adder (FA) The logical expression for is ：
F=A⊕B⊕Ci
Co=Ci(A⊕B)+AB
among A,B Is the number to add ,Ci Enter for carry ;F For and ,Co Is a carry output
The truth table is as follows ：
The schematic diagram is as follows ：
Therefore, when designing entities , Select three inputs and two outputs ：
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED; ENTITY
homework5 IS PORT( a,b,ci:IN STD_LOGIC; f,co:OUT STD_LOGIC ); END homework5;
ARCHITECTURE yejiayu OF homework5 IS BEGIN f<=(a XOR b)XOR ci; --F=A⊕B⊕Ci
co<=((a XOR b)AND ci)OR(a AND b); --Co=Ci(A⊕B)+AB END yejiayu;
Save the compiled simulation as follows ：
2. Four position full adder
（1） Implementation of component instantiation method ：
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY homework6 IS PORT( A0,A1,A2,A3,B0,B1,B2,B3:IN STD_LOGIC; F0,F1,F2,F3:OUT
STD_LOGIC; CI:IN STD_LOGIC; CO:OUT STD_LOGIC ); END homework6; ARCHITECTURE
yejiayu OF homework6 IS COMPONENT homework5 --COMPONENT Statement to implement the component instantiation method PORT(
a,b,ci:IN STD_LOGIC; f,co:OUT STD_LOGIC ); END COMPONENT homework5; SIGNAL
S0,S1,S2:STD_LOGIC; BEGIN U1:homework5 port map(A0,B0,CI,F0,S0); U2:homework5
port map(A1,B1,S0,F1,S1); U3:homework5 port map(A2,B2,S1,F2,S2); U4:homework5
port map(A3,B3,S2,F3,CO); END yejiayu;
Among them homework5 It is the entity file of the top one full adder
（ Next note !!!）
first , open quratusII Click Open homework5 file
Then new VHDL file , Write four bit full adder code , Save to the same folder （ Must be in the same folder !!!）
Then click before compiling settings Button change order （ Otherwise, the compiler is homework5 I fell right here ）
choice homework6
Then compile and simulate
（2） Simplify the implementation of four bit full adder
By calling STD_LOGIC_UNSIGNED In package “+” No. 1 method to design a 4 Bit full adder
The code is as follows ：
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY homework7 IS PORT( A,B:IN STD_LOGIC_VECTOR(3 DOWNTO 0); F:OUT
STD_LOGIC_VECTOR(4 DOWNTO 0)); END homework7; ARCHITECTURE yejiayu OF homework7
IS BEGIN PROCESS(A,B) BEGIN F<="00000"+A+B; END PROCESS; END yejiayu;
Compile simulation ：
ᵎ(•̀㉨•́)و ̑̑ come on.
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