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所谓内存时序,可以简单理解为内存的延迟
延迟越低,意味着CPU与内存交换数据间隔时间越短,性能相对越强
图中的 CL 18-22-22-42 即为时序
时序有四个参数 CAS - tRCD - tRP - tRAS,分别对应上图中所谓的CL 18-22-22-42
CPU在与内存交换数据,可以简要将内存理解为一个平面网状方格
CPU在寻址时,先确定所在的行,再确定所在的列,从而找到正确的数据
通过整个内存寻址过程,可以看出 tRAS = t选择数据所在行 + tRCD + (CL)CAS 这也是为什么时序最后一项比较高的原因
那真实的内存延迟怎么计算呢?
以DDR4 3200 C16 -18 - 18 - 36 为例:
频率3200Mhz指一个时钟周期(1s)工作3200M次,不难想到,产生延迟的主要原因实际上就是每次寻址的时间间隔(tRP)
真实内存延迟时间 = (1 / 频率) * tRP
前文提到,DDR内存的实际频率为等效频率的一半
也就是说 DDR4 3200 C16 -18 - 18 - 36 的真实内存延迟为:
1 / (1600 * 一百万) * tRP = 10ns
同理 DDR4 3600 C17 -17 - 18 - 39 的真实内存延迟 9.44ns
尽管时序较高,但频率越高,延迟实际也不见得更高
从上图不难看到,在DDR时代里,频率越来越高,相应的时序也越来越高,但实际上真正的延迟实际反而下降
(题外话:2021年 10 月底, DDR5 时代来临,威刚 DDR5 4800 C40 ,时序高得可怕)